The present disclosure relates generally to integrated circuit devices having high-speed (e.g., 1 Gbps or higher) transceivers and, more particularly, to devices with high-speed transceivers without dedicated phase-locked loop circuitry.
This section is intended to introduce the reader to various aspects of art that may be related to various aspects of the present disclosure, which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present disclosure. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.
Phase-locked loop (PLL) circuits are frequently employed by integrated circuit (IC) devices, such as a programmable logic device (PLD), to generate clock signals. In general, a PLL may be a feedback loop including a voltage-controlled oscillator (VCO) or a current-driven oscillator that outputs a clock signal. Oscillator control circuitry, which may include a phase frequency detector coupled to a charge pump, may compare the output clock signal to a reference clock signal and may drive the oscillator such that the output clock signal matches the phase and frequency of the reference clock signal. The output clock signal may enter a clock network of the IC device for distribution to data utilization circuitry, such as a field programmable gate array (FPGA) fabric.
Many IC devices employ general phase-locked loop (GPLL) circuits to generate global or regional clock signals. However, the clock signals output by such GPLL circuits may be insufficient for high-speed (e.g., greater than 1 Gbps) transceivers. Accordingly, such high-speed transceivers may typically include dedicated PLL circuits. These dedicated PLL circuits may generate clock signals sufficient to drive the high-speed transceivers, but may also take up additional die space, increasing manufacturing costs.